TRIP: Trainable Region-of-Interest Prediction for Hardware-Efficient Neuromorphic Processing on Event-Based Vision

Neuromorphic processors are well-suited for efficiently handling sparse events from event-based cameras. However, they face significant challenges in the growth of computing demand and hardware costs as the input resolution increases. This paper proposes the Trainable Region-of-Interest Prediction (...

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Vydáno v:2024 International Conference on Neuromorphic Systems (ICONS) s. 94 - 101
Hlavní autoři: Arjmand, Cina, Xu, Yingfu, Shidqi, Kevin, Dobrita, Alexandra F., Vadivel, Kanishkan, Detterer, Paul, Sifalakis, Manolis, Yousefzadeh, Amirreza, Tang, Guangzhi
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 30.07.2024
Témata:
Accuracy
Classification algorithms
Costs
digital neuromorphic processor
Event detection
event-based neural network
event-based vision
Faces
hard attention
Hardware
Neuromorphics
Optimization
Prediction algorithms
Program processors
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Shrnutí:Neuromorphic processors are well-suited for efficiently handling sparse events from event-based cameras. However, they face significant challenges in the growth of computing demand and hardware costs as the input resolution increases. This paper proposes the Trainable Region-of-Interest Prediction (TRIP)", the first hardware-efficient hard attention framework for event-based vision processing on a neuromorphic processor. Our TRIP framework actively produces low-resolution Region-of-Interest (ROIs) for efficient and accurate classification. The framework exploits sparse events' inherent low information density to reduce the overhead of ROI prediction. We introduced extensive hardware-aware optimizations for TRIP and implemented the hardware-optimized algorithm on the SENECA neuromorphic processor. We utilized multiple event-based classification datasets for evaluation. Our approach achieves state-of-the-art accuracies in all datasets and produces reasonable ROIs with varying locations and sizes. On the DvsGesture dataset, our solution requires 46× less computation than the state-of-the-art while achieving higher accuracy. Furthermore, TRIP enables more than 2× latency and energy improvements on the SENECA neuromorphic processor compared to the conventional solution.
DOI:10.1109/ICONS62911.2024.00022