Bus encoding for low-power high-performance memory systems

High-performance memory buses consume large energy as they include termination networks, BiCMOS and/or open-drain output. This paper introduces power reduction techniques for memory systems deliberating on burst-mode transfers over the high-speed bus specifications such as Low Voltage BiCMOS (LVT),...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:37th Design Automation Conference, 2000 S. 800 - 805
Hauptverfasser: Chang, Naehyuck, Kim, Kwanho, Cho, Jinsung
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: New York, NY, USA ACM 01.01.2000
IEEE
Schriftenreihe:ACM Conferences
Schlagworte:
Access protocols
Applied computing > Physical sciences and engineering > Engineering
BiCMOS integrated circuits
Cache memory
CMOS logic circuits
Computer systems organization > Dependable and fault-tolerant systems and networks
Encoding
Energy consumption
General and reference > Cross-computing tools and techniques > Performance
Hardware > Communication hardware, interfaces and storage > Buses and high-speed links
Hardware > Electronic design automation > Methodologies for EDA
Hardware > Emerging technologies
Hardware > Integrated circuits > Logic circuits > Arithmetic and datapath circuits
Hardware > Integrated circuits > Logic circuits > Design modules and hierarchy
Hardware > Robustness
Hardware > Very large scale integration design
Microprocessors
Networks > Network performance evaluation
Permission
Power system modeling
Random access memory
ISBN:9781581131871, 1581131879
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:High-performance memory buses consume large energy as they include termination networks, BiCMOS and/or open-drain output. This paper introduces power reduction techniques for memory systems deliberating on burst-mode transfers over the high-speed bus specifications such as Low Voltage BiCMOS (LVT), Gunning Transfer Logic (GTL+) and Stub Series Termination Logic (SSTL_2) which are widely used. The reduction techniques take both the static and the dynamic power consumption into account because most high-performance bus drivers and end-termination networks dissipate significant static power as well. Extensive performance analysis is conducted through mathematical analysis and trace data-driven simulations. We had reduction of 14% with random data and up to 67.5% with trace data.
Bibliographie:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9781581131871
1581131879
DOI:10.1145/337292.337778