Utilizing memory bandwidth in DSP embedded processors

This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently announced DSP processors, such as Star*core, sixteen bit instructions which simultaneously access four words from memory are supported. A polynom...

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Bibliographic Details
Published in:Design Automation, 2001 Proceedings pp. 347 - 352
Main Author: Gebotys, Catherine H.
Format: Conference Proceeding
Language:English
Published: New York, NY, USA ACM 01.01.2001
IEEE
Series:ACM Conferences
Subjects:
Applied computing > Physical sciences and engineering > Electronics
Applied computing > Physical sciences and engineering > Engineering
Bandwidth
Computer systems organization > Architectures
Computer systems organization > Dependable and fault-tolerant systems and networks
Computer systems organization > Embedded and cyber-physical systems
Computer systems organization > Real-time systems
Costs
Digital signal processing
Energy dissipation
General and reference > Cross-computing tools and techniques > Performance
Hardware > Electronic design automation > Methodologies for EDA
Hardware > Integrated circuits > Logic circuits > Arithmetic and datapath circuits
Hardware > Integrated circuits > Logic circuits > Design modules and hierarchy
High level languages
Intelligent networks
Networks > Network performance evaluation
Optimizing compilers
Permission
Power generation
Registers
ISBN:1581132972, 9781581132977
ISSN:0738-100X
Online Access:Get full text
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Summary:This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently announced DSP processors, such as Star*core, sixteen bit instructions which simultaneously access four words from memory are supported. A polynomial-time network flow methodology is used to allocate multiword accesses while minimizing code size. Results show that improvements of up to 87% in terms of memory bandwidth (and up to 30% reduction in energy dissipation) are obtained compared to compiler-generated DSP code. This research is important for industry since this value-added technique can increase memory bandwidths and minimize code size without increasing cost.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:1581132972
9781581132977
ISSN:0738-100X
DOI:10.1145/378239.378520