An O(m+n)-Space Spatiotemporal Denoising Filter with Cache-Like Memories for Dynamic Vision Sensors

Dynamic vision sensor (DVS) is novel neuromorphic imaging device that generates asynchronous events. Despite the high temporal resolution and high dynamic range features, DVS is faced with background noise problem. Spatiotemporal filter is an effective and hardware-friendly solution for DVS denoisin...

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Bibliographic Details
Published in:Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design pp. 1 - 9
Main Authors: Zhao, Qinghang, Wang, Jiaqi, Ji, Yixi, Wu, Jinjian, Shi, Guangming
Format: Conference Proceeding
Language:English
Published: ACM 27.10.2024
Subjects:
Denoising
Dynamic Vision Sensor
Field programmable gate arrays
FPGA
Memory architecture
Memory management
Noise reduction
Pipeline processing
Power demand
Real-time systems
Spatiotemporal Filter
Spatiotemporal phenomena
Vision sensors
Voltage control
ISSN:1558-2434
Online Access:Get full text
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Summary:Dynamic vision sensor (DVS) is novel neuromorphic imaging device that generates asynchronous events. Despite the high temporal resolution and high dynamic range features, DVS is faced with background noise problem. Spatiotemporal filter is an effective and hardware-friendly solution for DVS denoising but previous designs have large memory overhead or degraded performance issues. In this paper, we present a lightweight and real-time spatiotemporal denoising filter with set-associative cache-like memories, which has low space complexity of O(m+n) for DVS of m \times n resolution. A two-stage pipeline for memory access with read cancellation feature is proposed to reduce power consumption. Further the bitwidth redundancy for event storage is exploited to minimize the memory footprint. We implemented our design on FPGA and experimental results show that it achieves state-of-the-art performance compared with previous spatiotemporal filters while maintaining low resource utilization and low power consumption of about 125mW to 210mW at 100MHz clock frequency.
ISSN:1558-2434
DOI:10.1145/3676536.3676710