Parallel Incomplete LU Factorization Based Iterative Solver for Fixed-Structure Linear Equations in Circuit Simulation

A series of fixed-structure sparse linear equations are solved in a circuit simulation process. We propose a parallel incomplete LU (ILU) preconditioned GMRES solver for those equations. A new subtree-based scheduling algorithm for ILU factorization and forward/backward substitution is adopted to ov...

Celý popis

Uloženo v:
Podrobná bibliografie
Vydáno v:2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC) s. 339 - 345
Hlavní autoři: Li, Lingjie, Liu, Zhiqiang, Liu, Kan, Shen, Shan, Yu, Wenjian
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: New York, NY, USA ACM 16.01.2023
Edice:ACM Conferences
Témata:
Circuit simulation
Computing methodologies
Hardware
Hardware > Electronic design automation
Hardware > Electronic design automation > Physical design (EDA)
Hardware > Hardware validation
Hardware > Hardware validation > Functional verification
Hardware > Hardware validation > Functional verification > Simulation and emulation
Hardware > Integrated circuits
Hardware > Integrated circuits > Logic circuits
incomplete LU factorization
Iterative algorithms
iterative equation solver
Mathematical models
Matrices
Nonlinear circuits
parallel computing
Scheduling
Scheduling algorithms
Theory of computation
Theory of computation > Design and analysis of algorithms
circuit simulation
iterative equation solver
parallel computing
incomplete LU factorization
ISBN:9781450397834, 1450397832
ISSN:2153-697X
On-line přístup:Získat plný text
Tagy: Přidat tag
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
Popis
Shrnutí:A series of fixed-structure sparse linear equations are solved in a circuit simulation process. We propose a parallel incomplete LU (ILU) preconditioned GMRES solver for those equations. A new subtree-based scheduling algorithm for ILU factorization and forward/backward substitution is adopted to overcome the load-balancing and data locality problem of the conventional levelization-based scheduling. Experimental results show that the proposed scheduling algorithm can achieve up to 2.6X speedup for ILU factorization and 3.1X speedup for forward/backward substitution compared to the levelization-based scheduling. The proposed ILU-GMRES solver achieves around 4X parallel speedup with 8 threads, which is up to 2.1X faster than that based on the levelization-based scheme. The proposed parallel solver also shows remarkable advantage over existing methods (including HSPICE) on transient simulation of linear and nonlinear circuits.
ISBN:9781450397834
1450397832
ISSN:2153-697X
DOI:10.1145/3566097.3567882