Local Bayesian Optimization For Analog Circuit Sizing

This paper proposes a Bayesian Optimization (BO) algorithm to handle large-scale analog circuit sizing. The proposed approach uses a number of separate Gaussian Process (GP) models approximating the objective and constraint functions locally in the search space. Unlike mainstream BO approaches, it i...

Full description

Bibliographic Details

Published in:	2021 58th ACM/IEEE Design Automation Conference (DAC) pp. 1237 - 1242
Main Authors:	Touloupas, Konstantinos, Chouridis, Nikos, Sotiriadis, Paul P.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 05.12.2021
Subjects:	Analog circuits Bayes methods Design automation Focusing Gaussian processes Graphics processing units Search problems
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!