A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration

This paper presents a charge-sharing based customized 8T SRAM in-memory computing (IMC) architecture. In the proposed IMC approach, the multiply-accumulate (MAC) operation of multi-bit activations and weights is supported using the charge sharing between bit-line (BL) parasitic capacitances. The are...

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Veröffentlicht in:	2021 58th ACM/IEEE Design Automation Conference (DAC) S. 739 - 744
Hauptverfasser:	Lee, Kyeongho, Cheon, Sungsoo, Jo, Joongho, Choi, Woong, Park, Jongsun
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 05.12.2021
Schlagworte:	bit reconfigurable SAR-ADC Capacitance Capacitors charge domain compute compute-in-memory (CIM) Computer architecture Costs Energy efficiency In-memory computing (IMC) Random access memory Voltage
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