A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration

This paper presents a charge-sharing based customized 8T SRAM in-memory computing (IMC) architecture. In the proposed IMC approach, the multiply-accumulate (MAC) operation of multi-bit activations and weights is supported using the charge sharing between bit-line (BL) parasitic capacitances. The are...

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Bibliographic Details
Published in:2021 58th ACM/IEEE Design Automation Conference (DAC) pp. 739 - 744
Main Authors: Lee, Kyeongho, Cheon, Sungsoo, Jo, Joongho, Choi, Woong, Park, Jongsun
Format: Conference Proceeding
Language:English
Published: IEEE 05.12.2021
Subjects:
bit reconfigurable SAR-ADC
Capacitance
Capacitors
charge domain compute
compute-in-memory (CIM)
Computer architecture
Costs
Energy efficiency
In-memory computing (IMC)
Random access memory
Voltage
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Summary:This paper presents a charge-sharing based customized 8T SRAM in-memory computing (IMC) architecture. In the proposed IMC approach, the multiply-accumulate (MAC) operation of multi-bit activations and weights is supported using the charge sharing between bit-line (BL) parasitic capacitances. The area-efficient customized 8T SRAM macro can achieve robust and voltage-scalable MAC operations due to the charge-domain computation. We also propose a split capacitor structure-based 5/6-bit reconfigurable successive approximation register analog-to-digital converter (SAR-ADC) to reduce the hardware cost of an analog readout circuit while supporting higher precision MAC operations. The proposed reconfigurable SAR-ADC has been exploited to implement layer-by-layer mixed bit-precisions in convolution layer for increasing energy efficiency with negligible accuracy loss. The 256×64 8T SRAM IMC macro has been implemented using 28nm CMOS process technology. The proposed SRAM macro achieves 11. 20-TOPS/W with a maximum clock frequency of 125MHz at 1. 0V. It also supports supply voltage scaling from 0.5V to 1.1V with the energy efficiency ranging from 8.3-TOPS/W to 35.4-TOPS/W within 1 % accuracy loss.
DOI:10.1109/DAC18074.2021.9586103