Lower power by voltage stacking: A fine-grained system design approach

Stacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency of the power delivery. Previous works have shown voltage stacking at the core level only. In this paper we present a more involved approach...

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Vydané v:2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) s. 1 - 5
Hlavní autori: Blutman, Kristof, Kapoor, Ajay, Martinez, Jacinto Garcia, Fatemi, Hamed, de Gyvez, Jose Pineda
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 05.06.2016
Predmet:
charge recycling
Computer architecture
level shifter
low power design
microcontroller
Microcontrollers
Power conversion
Power demand
Regulators
Stacked circuits
Stacking
Voltage control
voltage regulator
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Shrnutí:Stacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency of the power delivery. Previous works have shown voltage stacking at the core level only. In this paper we present a more involved approach required to deploy voltage stacking not at the core level but at the IP level of a complex microcontroller. Our demonstrator chip features an ARM Cortex M0+ platform with an on-chip switched-capacitor voltage regulator. We chose to place the standard logic in one voltage domain between ground and V dd , and the memory "on top of it" between V dd and 2V dd , creating in this way a voltage stacked system. We further present silicon measurements that include a measured peak power efficiency in "stacked mode" of 96%.
DOI:10.1145/2897937.2898041