Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic

Systolic arrays provide a large amount of parallelism. However, their applicability is restricted to a small set of computational problems due to their lack of flexibility. This limitation can be circumvented by using reconfigurable systolic arrays, where the node interconnections and operations can...

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Bibliographic Details
Published in:Proceedings of the 17th symposium on Integrated circuits and system design pp. 248 - 253
Main Authors: Ayala-Rincón, Mauricio, Jacobi, Ricardo P., Carvalho, Luis G. A., Llanos, Carlos H., Hartenstein, Reiner W.
Format: Conference Proceeding
Language:English
Published: New York, NY, USA ACM 04.09.2004
IEEE
Series:ACM Conferences
Subjects:
Computer architecture
Context modeling
Digital systems
Dynamic programming
Parallel processing
Power system interconnection
Power system modeling
Prototypes
Systolic arrays
Theory of computation > Formal languages and automata theory > Formalisms > Rewrite systems
Theory of computation > Formal languages and automata theory > Grammars and context-free languages
Virtual prototyping
configware
dynamic programming
rewriting-logic
term rewriting systems (TRS)
reconfigurable systolic arrays
morphware
ISBN:1581139470, 9781581139471
Online Access:Get full text
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Summary:Systolic arrays provide a large amount of parallelism. However, their applicability is restricted to a small set of computational problems due to their lack of flexibility. This limitation can be circumvented by using reconfigurable systolic arrays, where the node interconnections and operations can be redefined even at run time. In this context, several alternative systolic architectures can be explored and powerful tools are needed to model and evaluate them. We show how well-known rewriting-logic environments could be used to quickly model and simulate complex application specific digital systems speeding-up its subsequent prototyping. We show how to use rewriting-logic to model and evaluate reconfigurable systolic architectures which are applied to the efficient treatment of several dynamic programming methods for resolving well-known problems such as global and local sequence alignment (Smith-Waterman algorithm), approximate string matching and computation of the longest common subsequence. A VHDL description of the conceived architecture was implemented from the rewriting-logic based abstract models and synthesized over an FPGA of the APEX family.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:1581139470
9781581139471
DOI:10.1145/1016568.1016634