Modular Verification of Safe Memory Reclamation in Concurrent Separation Logic

Formal verification is an effective method to address the challenge of designing correct and efficient concurrent data structures. But verification efforts often ignore memory reclamation, which involves nontrivial synchronization between concurrent accesses and reclamation. When incorrectly impleme...

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Veröffentlicht in:	Proceedings of ACM on programming languages Jg. 7; H. OOPSLA2; S. 828 - 856
Hauptverfasser:	Jung, Jaehwang, Lee, Janggun, Choi, Jaemin, Kim, Jaewoo, Park, Sunho, Kang, Jeehoon
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York, NY, USA ACM 16.10.2023
Schlagworte:	Concurrent algorithms Program verification Separation logic Theory of computation Iris safe memory reclamation separation logic
ISSN:	2475-1421, 2475-1421
Online-Zugang:	Volltext
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