On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing from provoking undesirable connections betwee...

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Vydané v:Design, Automation and Test in Europe s. 1290 - 1295
Hlavní autori: Kastensmidt, F. Lima, Sterpone, L., Carro, L., Reorda, M. Sonza
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: Washington, DC, USA IEEE Computer Society 07.03.2005
IEEE
Edícia:ACM Conferences
Predmet:
Circuit faults
Computer systems organization > Architectures > Other architectures > Reconfigurable computing
Computer systems organization > Architectures > Other architectures > Self-organizing autonomic computing
Fault tolerance
Field programmable gate arrays
Hardware > Hardware test
Hardware > Integrated circuits > Semiconductor memory > Static memory
Hardware > Robustness
Hardware > Very large scale integration design > Application-specific VLSI designs
Logic design
Protection
Redundancy
Robustness
Routing
Signal design
Signal generators
ISBN:9780769522883, 0769522882
ISSN:1530-1591
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Shrnutí:Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing from provoking undesirable connections between signals from distinct redundant logic parts, which can generate an error in the output. This paper investigates the optimal design of the TMR logic (e.g., by cleverly inserting voters) to ensure robustness. Four different versions of a TMR digital filter were analyzed by fault injection. Faults were randomly inserted straight into the bitstream of the FPGA. The experimental results presented in this paper demonstrate that the number and placement of voters in the TMR design can directly affect the fault tolerance, ranging from 4.03% to 0.98% the number of upsets in the routing able to cause an error in the TMR circuit.
Bibliografia:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9780769522883
0769522882
ISSN:1530-1591
DOI:10.1109/DATE.2005.229