Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters

This paper suggests a practical "hybrid" synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the circuit level. We show how to optimize stage-resolution to minimize the power in a pipelined ADC. Exploration...

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Vydané v:Design, Automation and Test in Europe s. 279 - 280
Hlavní autori: Chien, Yu-Tsun, Chen, Dong, Lou, Jea-Hong, Ma, Gin-Kou, Rutenbar, Rob A., Mukherjee, Tamal
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: Washington, DC, USA IEEE Computer Society 07.03.2005
IEEE
Edícia:ACM Conferences
Predmet:
Analog-digital conversion
Analytical models
Circuit simulation
Circuit synthesis
Circuit topology
CMOS process
Design methodology
Design optimization
Hardware > Hardware validation
Hardware > Hardware validation > Functional verification > Simulation and emulation
Hardware > Integrated circuits > Interconnect > Input > output circuits
Power system modeling
Semiconductor device modeling
ISBN:9780769522883, 0769522882
ISSN:1530-1591
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Shrnutí:This paper suggests a practical "hybrid" synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the circuit level. We show how to optimize stage-resolution to minimize the power in a pipelined ADC. Exploration (via detailed synthesis) of several ADC configurations is used to show that a 4-3-2... resolution distribution uses the least power for a 13-bit 40 MSPS converter in a 0.25 µm CMOS process.
Bibliografia:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9780769522883
0769522882
ISSN:1530-1591
DOI:10.1109/DATE.2005.119