Hardware Acceleration of Hidden Markov Model Decoding for Person Detection

This paper explores methods for hardware acceleration of Hidden Markov Model (HMM) decoding for the detection of persons in still images. Our architecture exploits the inherent structure of the HMM trellis to optimise a Viterbi decoder for extracting the state sequence from observation features. Fur...

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Vydané v:Design, Automation and Test in Europe s. 8 - 13
Hlavní autori: Fahmy, Suhaib A., Cheung, Peter Y. K., Luk, Wayne
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: Washington, DC, USA IEEE Computer Society 07.03.2005
IEEE
Edícia:ACM Conferences
Predmet:
Acceleration
Computer architecture
Computer systems organization > Architectures > Other architectures > Reconfigurable computing
Computer systems organization > Architectures > Other architectures > Self-organizing autonomic computing
Computing methodologies > Artificial intelligence > Computer vision > Computer vision problems > Object recognition
Concurrent computing
Decoding
Field programmable gate arrays
General and reference > Cross-computing tools and techniques > Performance
Hardware
Hardware > Very large scale integration design > Application-specific VLSI designs
Hardware > Very large scale integration design > Application-specific VLSI designs > Application specific processors
Hidden Markov models
Mathematics of computing > Probability and statistics > Probabilistic representations > Markov networks
Mathematics of computing > Probability and statistics > Stochastic processes > Markov processes
Parallel processing
Software performance
Theory of computation > Theory and algorithms for application domains > Machine learning theory > Markov decision processes
Viterbi algorithm
ISBN:9780769522883, 0769522882
ISSN:1530-1591
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Popis
Shrnutí:This paper explores methods for hardware acceleration of Hidden Markov Model (HMM) decoding for the detection of persons in still images. Our architecture exploits the inherent structure of the HMM trellis to optimise a Viterbi decoder for extracting the state sequence from observation features. Further performance enhancement is obtained by computing the HMM trellis states in parallel. The resulting hardware decoder architecture is mapped onto a field programmable gate array (FPGA). The performance and resource usage of our design is investigated for different levels of parallelism. Performance advantages over software are evaluated. We show how this work contributes to a real-time system for person-tracking in video-sequences.
Bibliografia:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9780769522883
0769522882
ISSN:1530-1591
DOI:10.1109/DATE.2005.169