Virtualizing Transactional Memory

Writing concurrent programs is difficult because of the complexity of ensuring proper synchronization. Conventional lock-based synchronization suffers from wellknown limitations, so researchers have considered non-blocking transactions as an alternative. Recent hardware proposals have demonstrated h...

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Bibliographic Details
Published in:32nd International Symposium on Computer Architecture (ISCA'05) pp. 494 - 505
Main Authors: Rajwar, Ravi, Herlihy, Maurice, Lai, Konrad
Format: Conference Proceeding
Language:English
Published: Washington, DC, USA IEEE Computer Society 01.05.2005
IEEE
Series:ACM Conferences
Subjects:
Computer architecture
Computing methodologies > Concurrent computing methodologies > Concurrent programming languages
Delay
Hardware
Hardware > Communication hardware, interfaces and storage
Hardware > Communication hardware, interfaces and storage > Buses and high-speed links
Hardware > Electronic design automation > High-level and register-transfer level synthesis
Hardware > Integrated circuits > Semiconductor memory
Microarchitecture
Programming profession
Proposals
Read-write memory
Scheduling
Software and its engineering > Software notations and tools > General programming languages > Language types > Concurrent programming languages
Switches
Theory of computation > Models of computation > Concurrency
Theory of computation > Models of computation > Concurrency > Parallel computing models
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ISBN:076952270X, 9780769522708
ISSN:1063-6897
Online Access:Get full text
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Summary:Writing concurrent programs is difficult because of the complexity of ensuring proper synchronization. Conventional lock-based synchronization suffers from wellknown limitations, so researchers have considered non-blocking transactions as an alternative. Recent hardware proposals have demonstrated how transactions can achieve high performance while not suffering limitations of lock-based mechanisms. However, current hardware proposals require programmers to be aware of platform-specific resource limitations such as buffer sizes, scheduling quanta, as well as events such as page faults, and process migrations. If the transactional model is to gain wide acceptance, hardware support for transactions must be virtualized to hide these limitations in much the same way that virtual memory shields the programmer from platform-specific limitations of physical memory. This paper proposes Virtual Transactional Memory (VTM), a user-transparent system that shields the programmer from various platform-specific resource limitations. VTM maintains the performance advantage of hardware transactions, incurs low overhead in time, and has modest costs in hardware support. While manysystem-level challenges remain, VTM takes a step toward making transactional models more widely acceptable.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:076952270X
9780769522708
ISSN:1063-6897
DOI:10.1109/ISCA.2005.54