A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms

Heterogeneous Multi-Processor SoC platforms bear the potential to optimize conflicting performance, flexibility and energy efficiency constraints as imposed by demanding signal processing and networking applications. However, in order to take advantage of the available processing and communication r...

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Bibliographic Details
Published in:Design, Automation and Test in Europe pp. 876 - 881
Main Authors: Kempf, Torsten, Doerper, Malte, Leupers, R., Ascheid, G., Meyr, H., Kogel, Tim, Vanthournout, Bart
Format: Conference Proceeding
Language:English
Published: Washington, DC, USA IEEE Computer Society 07.03.2005
IEEE
Series:ACM Conferences
Subjects:
Computer architecture
Computer systems organization > Architectures > Parallel architectures > Interconnection architectures
Computing methodologies > Modeling and simulation > Model development and analysis > Modeling methodologies
Data processing
Delay
General and reference > Cross-computing tools and techniques > Performance
Hardware
Hardware > Hardware validation > Functional verification > Simulation and emulation
Operating systems
Resource management
Resource virtualization
Signal processing
Software and its engineering > Software organization and properties > Contextual software domains > Operating systems > Process management > Multiprocessing > multiprogramming > multitasking
Space exploration
Theory of computation > Design and analysis of algorithms > Approximation algorithms analysis > Scheduling algorithms
Theory of computation > Design and analysis of algorithms > Online algorithms > Online learning algorithms > Scheduling algorithms
Theory of computation > Theory and algorithms for application domains > Machine learning theory > Reinforcement learning > Sequential decision making
Timing
ISBN:9780769522883, 0769522882
ISSN:1530-1591
Online Access:Get full text
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Summary:Heterogeneous Multi-Processor SoC platforms bear the potential to optimize conflicting performance, flexibility and energy efficiency constraints as imposed by demanding signal processing and networking applications. However, in order to take advantage of the available processing and communication resources, an optimal mapping of the application tasks onto the platform resources is of crucial importance. In this paper, we propose a SystemC-based simulation framework, which enables the quantitative evaluation of application-to-platform mappings by means of an executable performance model. Key element of our approach is a configurable event-driven Virtual Processing Unit to capture the timing behavior of multi-processor/multi-threaded MP-SoC platforms. The framework features an XML-based declarative construction mechanism of the performance model to significantly accelerate the navigation in large design spaces. The capabilities of the proposed framework in terms of design space exploration is presented by a case study of a commercially available MP-SoC platform for networking applications. Focussing on the application to architecture mapping, our introduced framework highlights the potential for optimization of an efficient design space exploration environment.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9780769522883
0769522882
ISSN:1530-1591
DOI:10.1109/DATE.2005.21