Architectural synthesis of performance-driven multipliers with accumulator interleaving

VLSI multipliers assume different characteristics in terms of latency, throughput and area for different target applications. This paper proposes a methodology of automatically generating a multiplier from the user's specifications of latency, throughput, and area. The entire gamut of multiplie...

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Vydáno v:30th ACM/IEEE Design Automation Conference s. 303 - 307
Hlavní autoři: Ghosh, Debabrata, Nandy, S. K., Sadayappan, P., Parthasarathy, K.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: New York, NY, USA ACM 01.07.1993
Edice:ACM Conferences
Témata:
Database machines
Delay
Design methodology
Hardware > Electronic design automation > High-level and register-transfer level synthesis
Hardware > Electronic design automation > High-level and register-transfer level synthesis > Datapath optimization
Hardware > Electronic design automation > Logic synthesis > Circuit optimization
Hardware > Integrated circuits > Logic circuits > Arithmetic and datapath circuits
Hardware > Very large scale integration design
Hardware > Very large scale integration design > VLSI packaging > Input > output styles
Instruments
Interleaved codes
Logic
Pipeline processing
Space technology
Throughput
Very large scale integration
ISBN:9780897915779, 0897915771
ISSN:0738-100X
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Shrnutí:VLSI multipliers assume different characteristics in terms of latency, throughput and area for different target applications. This paper proposes a methodology of automatically generating a multiplier from the user's specifications of latency, throughput, and area. The entire gamut of multipliers, starting from low area, moderate performance multipliers to high performance ones with low latency and/or very high throughput is captured in this synthesis procedure. The architecture comprises of a smaller core, a Front End Server (FES) and a Back End Processor (BEP) which allows to use the basic core repetitively for multiplication of larger numbers. Through a novel method of accumulator interleaving the multipliers designed using the proposed methodology support better performance compared to conventional approaches. The proposed methodology can be used for synthesis of multipliers occupying any place (feasible in a given technology) in the A - L - T (Area, Latency, Throughput) space, subject to an affordable power dissipation.
Bibliografie:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9780897915779
0897915771
ISSN:0738-100X
DOI:10.1145/157485.164902