A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation

Many partitioning algorithms have been proposed for distributed VLSI simulation. Typically, they make use of a gate level netlist, and attempt to achieve a minimal cut size subject to a load balance constraint. The algorithm executes on a hypergraph which represents the netlist. In this paper we pro...

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Bibliographic Details
Published in:	21st International Workshop on Principles of Advanced and Distributed Simulation (PADS 2007): San Diego, California - 12-15 June 2007 pp. 211 - 218
Main Authors:	Li, Lijun, Tropper, Carl
Format:	Conference Proceeding
Language:	English
Published:	Washington, DC, USA IEEE Computer Society 12.06.2007 IEEE
Series:	ACM Conferences
Subjects:	Algorithm design and analysis Circuit simulation Clustering algorithms Computational modeling Costs Hardware > Hardware validation > Functional verification > Simulation and emulation Hardware > Integrated circuits > Logic circuits Hardware design languages Iterative algorithms Load management Partitioning algorithms Very large scale integration
ISBN:	9780769528984, 0769528988
ISSN:	1087-4097
Online Access:	Get full text
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