A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation

Many partitioning algorithms have been proposed for distributed VLSI simulation. Typically, they make use of a gate level netlist, and attempt to achieve a minimal cut size subject to a load balance constraint. The algorithm executes on a hypergraph which represents the netlist. In this paper we pro...

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Veröffentlicht in:21st International Workshop on Principles of Advanced and Distributed Simulation (PADS 2007): San Diego, California - 12-15 June 2007 S. 211 - 218
Hauptverfasser: Li, Lijun, Tropper, Carl
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: Washington, DC, USA IEEE Computer Society 12.06.2007
IEEE
Schriftenreihe:ACM Conferences
Schlagworte:
Algorithm design and analysis
Circuit simulation
Clustering algorithms
Computational modeling
Costs
Hardware > Hardware validation > Functional verification > Simulation and emulation
Hardware > Integrated circuits > Logic circuits
Hardware design languages
Iterative algorithms
Load management
Partitioning algorithms
Very large scale integration
ISBN:9780769528984, 0769528988
ISSN:1087-4097
Online-Zugang:Volltext
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Zusammenfassung:Many partitioning algorithms have been proposed for distributed VLSI simulation. Typically, they make use of a gate level netlist, and attempt to achieve a minimal cut size subject to a load balance constraint. The algorithm executes on a hypergraph which represents the netlist. In this paper we propose a design-driven iterative partitioning algorithm for Verilog based on module instances instead of gates. We do this in order to take advantage of the design hierarchy information contained in the modules and their instances. A Verilog instance represents one vertex in the circuit hypergraph. The vertex can be flattened into multiple vertices in the event that a load balance is not achieved by instance based partitioning. In this case the algorithm flattens the largest instance and moves gates between the partitions in order to improve the load balance. Our experiments show that this partitioning algorithm produces a smaller cutsize than is produced by hmetis on a gate-level netlist. It produces better speedup for the simulation because it takes advantage of the design hierarchy.
Bibliographie:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9780769528984
0769528988
ISSN:1087-4097
DOI:10.1109/PADS.2007.4