High-Performance Computing Architecture Exploration with Stage-Enhanced Bayesian Optimization

The emergence of new applications in high-performance computing is driving the need for more efficient computing machines. As supercomputer architectures become increasingly complex, the combinatorial explosion of design spaces and the time-consuming nature of design simulations lead to challenging...

Celý popis

Uložené v:
Podrobná bibliografia
Vydané v:2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7
Hlavní autori: Fu, Vincent, Benazouz, Mohamed, Zaourar, Lilia, Munier-Kordon, Alix
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 22.06.2025
Predmet:
Bayes methods
Bayesian optimization
Computational modeling
Computer architecture
Design automation
design space exploration
Ensemble learning
Explosions
High performance computing
Optimization
Space exploration
Supercomputers
On-line prístup:Získať plný text
Tagy: Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
Popis
Shrnutí:The emergence of new applications in high-performance computing is driving the need for more efficient computing machines. As supercomputer architectures become increasingly complex, the combinatorial explosion of design spaces and the time-consuming nature of design simulations lead to challenging design space exploration problems. This work introduces an automated search framework to achieve power-performance-area efficient Arm Neoverse V1 processor designs. Based on multi-objective Bayesian optimization, we propose a new exploration algorithm named SEBO by enhancing the three main stages of the optimization. Experimental results show that SEBO can not only compete with the top state-of-the-art baseline algorithms, but also outperforms them in terms of the quality and diversity of the returned Pareto-optimal designs.
DOI:10.1109/DAC63849.2025.11132525