High-Performance Computing Architecture Exploration with Stage-Enhanced Bayesian Optimization

The emergence of new applications in high-performance computing is driving the need for more efficient computing machines. As supercomputer architectures become increasingly complex, the combinatorial explosion of design spaces and the time-consuming nature of design simulations lead to challenging...

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Bibliographic Details
Published in:2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 7
Main Authors: Fu, Vincent, Benazouz, Mohamed, Zaourar, Lilia, Munier-Kordon, Alix
Format: Conference Proceeding
Language:English
Published: IEEE 22.06.2025
Subjects:
Bayes methods
Bayesian optimization
Computational modeling
Computer architecture
Design automation
design space exploration
Ensemble learning
Explosions
High performance computing
Optimization
Space exploration
Supercomputers
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Summary:The emergence of new applications in high-performance computing is driving the need for more efficient computing machines. As supercomputer architectures become increasingly complex, the combinatorial explosion of design spaces and the time-consuming nature of design simulations lead to challenging design space exploration problems. This work introduces an automated search framework to achieve power-performance-area efficient Arm Neoverse V1 processor designs. Based on multi-objective Bayesian optimization, we propose a new exploration algorithm named SEBO by enhancing the three main stages of the optimization. Experimental results show that SEBO can not only compete with the top state-of-the-art baseline algorithms, but also outperforms them in terms of the quality and diversity of the returned Pareto-optimal designs.
DOI:10.1109/DAC63849.2025.11132525