Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore

Existing tiled manycore architectures propose to convert abundant silicon resources into general-purpose parallel processors with unmatched computational density and programmability. However, as we approach 100 K cores in one chip, conventional manycore architectures struggle to navigate three key a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA) S. 770 - 784
Hauptverfasser: Jung, Dai Cheol, Ruttenberg, Max, Gao, Paul, Davidson, Scott, Petrisko, Daniel, Li, Kangli, Kamath, Aditya K, Cheng, Lin, Xie, Shaolin, Pan, Peitian, Zhao, Zhongyuan, Yue, Zichao, Veluri, Bandhav, Muralitharan, Sripathi, Sampson, Adrian, Lumsdaine, Andrew, Zhang, Zhiru, Batten, Christopher, Oskin, Mark, Richmond, Dustin, Taylor, Michael Bedford
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 29.06.2024
Schlagworte:
Computer architecture
Instruction sets
manycore architecture
open-source hardware
Parallel processing
parallel programming
RISC-V
Scalability
Silicon
Source coding
Voltage
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Existing tiled manycore architectures propose to convert abundant silicon resources into general-purpose parallel processors with unmatched computational density and programmability. However, as we approach 100 K cores in one chip, conventional manycore architectures struggle to navigate three key axes: scalability, programmability, and density. Many manycores sacrifice programmability for density; or scalability for programmability. In this paper, we explore HammerBlade, which simultaneously achieves scalability, programmability and density. HammerBlade is a fully open-source RISC-V manycore architecture, which has been silicon-validated with a 2048-core ASIC implementation using a 14/16nm process. We evaluate the system using a suite of parallel benchmarks that captures a broad spectrum of computation and communication patterns.
DOI:10.1109/ISCA59077.2024.00061