Improved heuristics for finite word-length polynomial datapath optimization
Conventional high-level synthesis techniques are not able to manipulate polynomial expressions efficiently due to the lack of suitable optimization techniques for redundancy elimination over Z 2 n . This paper, in comparison with, presents 1) an improved partitioning heuristic based on single-variab...
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| Published in: | 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers pp. 739 - 744 |
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| Main Authors: | , |
| Format: | Conference Proceeding |
| Language: | English Japanese |
| Published: |
IEEE
02.11.2009
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| Subjects: | |
| ISSN: | 1092-3152 |
| Online Access: | Get full text |
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| Summary: | Conventional high-level synthesis techniques are not able to manipulate polynomial expressions efficiently due to the lack of suitable optimization techniques for redundancy elimination over Z 2 n . This paper, in comparison with, presents 1) an improved partitioning heuristic based on single-variable monomials instead of checking all sub-polynomials, 2) an improved compensation heuristic which is able to compensate monomials as well as coefficients, and 3) a combined area-delay-optimized factorization approach to extract the most frequently used sub-expressions from multi-output polynomials over Z 2 n . Experimental results have shown an average saving of 32% and 27.2% in the number of logic gates and critical path delay respectively compared to the state-of-the-art techniques. Regarding the comparison with, the number of gates and delay are improved by 14.3% and 13.9% respectively. Furthermore, the results show that the combined area-delay optimization can reduce the average delay by 26.4%. |
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| ISSN: | 1092-3152 |
| DOI: | 10.1145/1687399.1687536 |