Web-Based Simulator of Superscalar RISC-V Processors

Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar RISC-V processors, HW/SW co-design and HPC optimization techniques. With customizable proce...

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Bibliographische Detailangaben

Veröffentlicht in:	SC24-W: Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis S. 1676 - 1684
Hauptverfasser:	Jaros, Jiri, Majer, Michal, Horky, Jakub, Vavra, Jan
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 17.11.2024
Schlagworte:	Codes Computer architecture HW-SW Co-design Optimization Processor Simulator Program processors RISC-V Runtime Semiconductor device measurement Software development management Source coding Superscalar Processor Systems architecture Vectors Web Application
Online-Zugang:	Volltext
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