Procedure placement using temporal ordering information

Instruction cache performance is very important to instruction fetch efficiency and overall processor performance. The layout of an executable has a substantial effect on the cache miss rate during execution. This means that the performance of an executable can be improved significantly by applying...

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Bibliographic Details
Published in:	Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture pp. 303 - 313
Main Authors:	Gloy, Nikolas, Blackwell, Trevor, Smith, Michael D., Calder, Brad
Format:	Conference Proceeding Journal Article
Language:	English
Published:	Washington, DC, USA IEEE Computer Society 01.01.1997
Series:	ACM Conferences
Subjects:	Computer systems organization > Architectures > Parallel architectures > Very long instruction word Computer systems organization > Architectures > Serial architectures > Complex instruction set computing Computer systems organization > Architectures > Serial architectures > Reduced instruction set computing Computer systems organization > Dependable and fault-tolerant systems and networks General and reference > Cross-computing tools and techniques > Performance Mathematics of computing > Information theory Mathematics of computing > Information theory > Coding theory Mathematics of computing > Mathematical software Networks > Network performance evaluation Security and privacy > Cryptography > Mathematical foundations of cryptography code layout conflict misses profiling
ISBN:	0818679778, 9780818679773
ISSN:	1072-4451
Online Access:	Get full text
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