Performance of cached DRAM organizations in vector supercomputers

DRAMs containing cache memory are studied in the context of vector supercomputers. In particular, we consider systems where processors have no internal data caches and memory reference streams are generated by vector instructions. For this application, we expect that cached DRAMs can provide high ba...

Full description

Saved in:

Bibliographic Details
Published in:	Computer Architecture, 20th International Symposium (ISCA "93) pp. 327 - 336
Main Authors:	Hsu, W.-C., Smith, J. E.
Format:	Conference Proceeding
Language:	English
Published:	New York, NY, USA ACM 01.05.1993
Series:	ACM Conferences
Subjects:	Computer systems organization > Architectures > Distributed architectures > Grid computing Computer systems organization > Architectures > Parallel architectures > Multicore architectures Computer systems organization > Architectures > Parallel architectures > Systolic arrays Computer systems organization > Architectures > Serial architectures > Superscalar architectures Computing methodologies > Modeling and simulation > Model development and analysis > Modeling methodologies Computing methodologies > Modeling and simulation > Simulation types and techniques > Massively parallel and high-performance simulations General and reference > Cross-computing tools and techniques > Performance Software and its engineering > Software organization and properties > Software system structures > Distributed systems organizing principles > Grid computing
ISBN:	0818638109, 9780818638107
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

Be the first to leave a comment!