Performance of cached DRAM organizations in vector supercomputers

DRAMs containing cache memory are studied in the context of vector supercomputers. In particular, we consider systems where processors have no internal data caches and memory reference streams are generated by vector instructions. For this application, we expect that cached DRAMs can provide high ba...

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Vydáno v:Computer Architecture, 20th International Symposium (ISCA "93) s. 327 - 336
Hlavní autoři: Hsu, W.-C., Smith, J. E.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: New York, NY, USA ACM 01.05.1993
Edice:ACM Conferences
Témata:
Computer systems organization > Architectures > Distributed architectures > Grid computing
Computer systems organization > Architectures > Parallel architectures > Multicore architectures
Computer systems organization > Architectures > Parallel architectures > Systolic arrays
Computer systems organization > Architectures > Serial architectures > Superscalar architectures
Computing methodologies > Modeling and simulation > Model development and analysis > Modeling methodologies
Computing methodologies > Modeling and simulation > Simulation types and techniques > Massively parallel and high-performance simulations
General and reference > Cross-computing tools and techniques > Performance
Software and its engineering > Software organization and properties > Software system structures > Distributed systems organizing principles > Grid computing
ISBN:0818638109, 9780818638107
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Shrnutí:DRAMs containing cache memory are studied in the context of vector supercomputers. In particular, we consider systems where processors have no internal data caches and memory reference streams are generated by vector instructions. For this application, we expect that cached DRAMs can provide high bandwidth at relatively low cost. We study both DRAMs with a single, long cache line and with smaller, multiple cache lines. Memory interleaving schemes that increase data locality are proposed and studied. The interleaving schemes are also shown to lead to non-uniform bank accesses, i.e. hot banks. This suggest there is an important optimization problem involving methods that increase locality to improve performance, but not so much that hot banks diminish performance. We show that for uniprocessor systems, both types of cached DRAMs work well with the proposed interleave methods. For multiprogrammed multiprocessors, the multiple cache line DRAMs work better.
Bibliografie:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:0818638109
9780818638107
DOI:10.1145/165123.165170