TransSizer: A Novel Transformer-Based Fast Gate Sizer

Gate sizing is a fundamental netlist optimization move and researchers have used supervised learning-based models in gate sizers. Recently, Reinforcement Learning (RL) has been tried for sizing gates (and other EDA optimization problems) but are very runtime-intensive. In this work, we explore a nov...

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Veröffentlicht in:	2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) S. 1 - 9
Hauptverfasser:	Nath, Siddhartha, Pradipta, Geraldo, Hu, Corey, Yang, Tian, Khailany, Brucek, Ren, Haoxing
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	ACM 29.10.2022
Schlagworte:	Computational modeling Computer architecture Data models generative model Logic gates Measurement Netlist optimization sizing Training Transformer Transformers
ISSN:	1558-2434
Online-Zugang:	Volltext
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