DEEP: Developing Extremely Efficient Runtime On-Chip Power Meters

Accurate and efficient on-chip power modeling is crucial to runtime power, energy, and voltage management. Such power monitoring can be achieved by designing and integrating on-chip power meters (OPMs) into the target design. In this work, we propose a new method named DEEP to automatically develop...

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Vydané v:2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) s. 1 - 9
Hlavní autori: Xie, Zhiyao, Li, Shiyu, Ma, Mingyuan, Chang, Chen-Chia, Pan, Jingyu, Chen, Yiran, Hu, Jiang
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: ACM 29.10.2022
Predmet:
Costs
Estimation
Layout
Meters
Microprocessors
Runtime
Voltage
ISSN:1558-2434
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Popis
Shrnutí:Accurate and efficient on-chip power modeling is crucial to runtime power, energy, and voltage management. Such power monitoring can be achieved by designing and integrating on-chip power meters (OPMs) into the target design. In this work, we propose a new method named DEEP to automatically develop extremely efficient OPM solutions for a given design. DEEP selects OPM inputs from all individual bits in RTL signals. Such bit-level selection provides an unprecedentedly large number ofinput candidates and supports lower hardware cost, compared with signal-level selection in prior works. In addition, DEEP proposes a powerful two-step OPM input selection method, and it supports reporting both total power and the power of major design components. Experiments on a commercial microprocessor demonstrate that DEEP's OPM solution achieves correlation R > 0.97 in per-cycle power prediction with an unprecedented low area overhead on hardware, i.e., < 0.1% of the microprocessor layout. This reduces the OPM hardware cost by 4 - 6× compared with the state-of-the-art solution.
ISSN:1558-2434
DOI:10.1145/3508352.3549427