Applying GNNs to Timing Estimation at RTL : (Invited Paper)

In the Electronic Design Automation (EDA) flow, signoff checks, such as timing analysis, are performed only after physical synthesis. Encountered timing violations cause re-iterations of the design flow. Hence, timing estimations at initial design stages, such as Register Transfer Level (RTL), would...

Celý popis

Podrobná bibliografia

Vydané v:	2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) s. 1 - 8
Hlavní autori:	Lopera, Daniela Sanchez, Ecker, Wolfgang
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	ACM 29.10.2022
Predmet:	Computer architecture Delay Delays Design automation Electronic Design Automation Estimation Graph Neural Networks Measurement Register Transfer Level Slew Timing Analysis Topology Training data
ISSN:	1558-2434
On-line prístup:	Získať plný text
Tagy:	Pridať tag Žiadne tagy, Buďte prvý, kto otaguje tento záznam!