Load value prediction via path-based address prediction avoiding mispredictions due to conflicting stores

Current flagship processors excel at extracting instruction-level-parallelism (ILP) by forming large instruction windows. Even then, extracting ILP is inherently limited by true data dependencies. Value prediction was proposed to address this limitation. Many challenges face value prediction, in thi...

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Veröffentlicht in:	MICRO-50 : the 50th annual IEEE/ACM International Symposium on Microarchitecture : proceedings : October 14-18, 2017, Cambridge, MA S. 423 - 435
Hauptverfasser:	Sheikh, Rami, Cain, Harold W., Damodaran, Raguram
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	New York, NY, USA ACM 14.10.2017
Schriftenreihe:	ACM Conferences
Schlagworte:	Address Prediction Computer systems organization > Architectures > Serial architectures > Pipeline computing Computer systems organization > Architectures > Serial architectures > Reduced instruction set computing Computer systems organization > Architectures > Serial architectures > Superscalar architectures History Machinery Microarchitecture Path-based Predictor Pipelines Prefetching Registers Value Prediction value prediction address prediction path-based predictor microarchitecture
ISBN:	1450349528, 9781450349529
ISSN:	2379-3155
Online-Zugang:	Volltext
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