Student research poster: A low complexity cache sharing mechanism to address system fairness
Shared caches have become, de facto, the common design choice in current multi-cores, ranging from embedded devices to high-performance processors. In these systems, requests from multiple applications compete for the cache resources, degrading to different extents their progress, quantified as the...
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| Veröffentlicht in: | 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT) S. 455 |
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| Format: | Tagungsbericht |
| Sprache: | Englisch |
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ACM
01.09.2016
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| Abstract | Shared caches have become, de facto, the common design choice in current multi-cores, ranging from embedded devices to high-performance processors. In these systems, requests from multiple applications compete for the cache resources, degrading to different extents their progress, quantified as the performance of individual applications compared to isolated execution. The difference between the progresses of the running applications yields the system to unpredictable behavior and causes a fairness problem. This problem can be addressed by carefully partitioning cache resources among the contending applications, but to be effective, a partitioning approach needs to estimate the per-application progress. |
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| AbstractList | Shared caches have become, de facto, the common design choice in current multi-cores, ranging from embedded devices to high-performance processors. In these systems, requests from multiple applications compete for the cache resources, degrading to different extents their progress, quantified as the performance of individual applications compared to isolated execution. The difference between the progresses of the running applications yields the system to unpredictable behavior and causes a fairness problem. This problem can be addressed by carefully partitioning cache resources among the contending applications, but to be effective, a partitioning approach needs to estimate the per-application progress. |
| Author | Gomez, Maria E. Selfa, Vicent Petit, Salvador Sahuquillo, Julio |
| Author_xml | – sequence: 1 givenname: Vicent surname: Selfa fullname: Selfa, Vicent email: viselol@disca.upv.es organization: Dept. of Comput. Eng., Univ. Politec. de Valencia, Valencia, Spain – sequence: 2 givenname: Julio surname: Sahuquillo fullname: Sahuquillo, Julio organization: Dept. of Comput. Eng., Univ. Politec. de Valencia, Valencia, Spain – sequence: 3 givenname: Salvador surname: Petit fullname: Petit, Salvador organization: Dept. of Comput. Eng., Univ. Politec. de Valencia, Valencia, Spain – sequence: 4 givenname: Maria E. surname: Gomez fullname: Gomez, Maria E. organization: Dept. of Comput. Eng., Univ. Politec. de Valencia, Valencia, Spain |
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| Snippet | Shared caches have become, de facto, the common design choice in current multi-cores, ranging from embedded devices to high-performance processors. In these... |
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| SubjectTerms | Binary trees Complexity theory Computers Distance measurement Performance evaluation Program processors Runtime |
| Title | Student research poster: A low complexity cache sharing mechanism to address system fairness |
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