Energy-efficient XNOR-free In-Memory BNN Accelerator with Input Distribution Regularization

SRAM-based in-memory Binary Neural Network (BNN) accelerators are garnering interests as a platform for energy-efficient edge neural network computing thanks to their compactness in terms of hardware and neural network parameter size. However, previous works had to modify SRAM cells to support XNOR...

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Veröffentlicht in:	Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design S. 1 - 9
Hauptverfasser:	Kim, Hyungjun, Oh, Hyunmyung, Kim, Jae-Joon
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	Association on Computer Machinery 02.11.2020
Schlagworte:	binary input data computation error Computational modeling conventional 6T SRAM arrays conversion method energy conservation Energy consumption Energy efficiency energy-efficient edge neural network computing energy-efficient XNOR-free in-memory BNN accelerator Handheld computers inference energy efficiency input distribution regularization memory array network training neural chips neural network parameter size SRAM cells SRAM chips SRAM-based in-memory binary neural network accelerators Training Transistors XNOR operations
ISSN:	1558-2434
Online-Zugang:	Volltext
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