Energy-efficient XNOR-free In-Memory BNN Accelerator with Input Distribution Regularization

SRAM-based in-memory Binary Neural Network (BNN) accelerators are garnering interests as a platform for energy-efficient edge neural network computing thanks to their compactness in terms of hardware and neural network parameter size. However, previous works had to modify SRAM cells to support XNOR...

Celý popis

Uloženo v:

Podrobná bibliografie
Vydáno v:	Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design s. 1 - 9
Hlavní autoři:	Kim, Hyungjun, Oh, Hyunmyung, Kim, Jae-Joon
Médium:	Konferenční příspěvek
Jazyk:	angličtina
Vydáno:	Association on Computer Machinery 02.11.2020
Témata:	binary input data computation error Computational modeling conventional 6T SRAM arrays conversion method energy conservation Energy consumption Energy efficiency energy-efficient edge neural network computing energy-efficient XNOR-free in-memory BNN accelerator Handheld computers inference energy efficiency input distribution regularization memory array network training neural chips neural network parameter size SRAM cells SRAM chips SRAM-based in-memory binary neural network accelerators Training Transistors XNOR operations
ISSN:	1558-2434
On-line přístup:	Získat plný text
Tagy:	Přidat tag Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!

Buďte první, kdo okomentuje tento záznam!