ILP and TLP in shared memory applications: A limit study

With the breakdown of Dennard scaling, future processor designs will be at the mercy of power limits as Chip MultiProcessor (CMP) designs scale out to many-cores. It is critical, therefore, that future CMPs be optimally designed in terms of performance efficiency with respect to power. A characteriz...

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Veröffentlicht in:	PACT '14 : proceedings of the 23rd International Conference on Parallel Architectures and Compilation Techniques : August 24-27, 2014, Edmonton, AB, Canada S. 113 - 125
Hauptverfasser:	Fatehi, Ehsan, Gratz, Paul V.
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	ACM 01.08.2014
Schlagworte:	Benchmark testing Instruction sets Instruction-Level Parallelism (ILP) Limits Multicore processing Parallel processing PThreads Thread-Level Parallelism (TLP) Transistors Upper bound
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