Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks

Modern heterogeneous FPGA architectures incorporate a variety of hardened blocks for boosting the performance of arithmetic-intensive designs, such as DSP blocks and carry blocks. Since hardened blocks can be configured in different ways, a variety of datapath patterns can be mapped into these block...

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Bibliographic Details
Published in:Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design pp. 1 - 9
Main Authors: Ustun, Ecenur, Deng, Chenhui, Pal, Debjit, Li, Zhijing, Zhang, Zhiru
Format: Conference Proceeding
Language:English
Published: Association on Computer Machinery 02.11.2020
Subjects:
Adders
arithmetic-intensive designs
Computer architecture
datapath patterns
delay estimation
DSP blocks
field programmable gate arrays
FPGA HLS
GNN models
graph neural networks
graph theory
high level synthesis
inductive learning
learning (artificial intelligence)
modern heterogeneous FPGA architectures
neural nets
operation delay prediction
operation mapping patterns
Optimization
resource usage
Task analysis
ISSN:1558-2434
Online Access:Get full text
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Summary:Modern heterogeneous FPGA architectures incorporate a variety of hardened blocks for boosting the performance of arithmetic-intensive designs, such as DSP blocks and carry blocks. Since hardened blocks can be configured in different ways, a variety of datapath patterns can be mapped into these blocks. We observe that existing high-level synthesis (HLS) tools often fail to capture some of the operation mapping patterns, leading to limited estimation accuracy in terms of resource usage and delay. To address this deficiency, we propose to exploit graph neural networks (GNN) to automatically learn operation mapping patterns. We apply GNN models that are trained on microbenchmarks directly to realistic designs through inductive learning. Experimental results show that our approach can effectively infer various valid mapping patterns on both microbenchmarks and realistic designs. Furthermore, the proposed framework is exploited to improve the accuracy of delay estimation in HLS.
ISSN:1558-2434
DOI:10.1145/3400302.3415657