Minimizing area and power of sequential CMOS circuits using threshold decomposition

This paper describes the design of a standard cell library of differential mode threshold gates, referred to as a Threshold Logic Latch or TLL, and new threshold function identification and decomposition methods to map a conventional logic network consisting of logic gates and flipflops, into a hybr...

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Bibliographic Details
Published in:2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) pp. 605 - 612
Main Authors: Kulkarni, Niranjan, Nukala, Nishant, Vrudhula, Sarma
Format: Conference Proceeding
Language:English
Published: New York, NY, USA ACM 05.11.2012
IEEE
Series:ACM Conferences
Subjects:
Boolean Decomposition
Boolean functions
Data structures
Delay
Dynamic Power
Hardware > Integrated circuits > Logic circuits > Sequential circuits
Leakage Power
Libraries
Logic gates
Microprocessors
Sequential Circuits
Technology Mapping
Threshold Logic
TLL
technology mapping
TLL
boolean decomposition
sequential circuits
dynamic power
threshold logic
leakage power
ISBN:9781450315739, 1450315739
ISSN:1092-3152
Online Access:Get full text
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Summary:This paper describes the design of a standard cell library of differential mode threshold gates, referred to as a Threshold Logic Latch or TLL, and new threshold function identification and decomposition methods to map a conventional logic network consisting of logic gates and flipflops, into a hybrid network that consists of both TLLs and conventional logic gates. After logic synthesis and physical design (placement and routing) using a commercial 65nm LP (low power) library, and commercial design tools, the hybrid circuits are shown to have up to 35% less dynamic power, about 50% less leakage power and around 37% less area when compared to the corresponding conventional design operated at the same (peak) frequency.
ISBN:9781450315739
1450315739
ISSN:1092-3152
DOI:10.1145/2429384.2429514