Achieving Out-of-Order Performance with Almost In-Order Complexity

There is still much performance to be gained by out-of-order processors with wider issue widths. However, traditional methods of increasing issue width do not scale; that is, they drastically increase design complexity and power requirements. This paper introduces the braid, a compile-time identifie...

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Veröffentlicht in:	2008 International Symposium on Computer Architecture S. 3 - 12
Hauptverfasser:	Tseng, Francis, Patt, Yale N.
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	Washington, DC, USA IEEE Computer Society 01.06.2008 IEEE
Schriftenreihe:	ACM Conferences
Schlagworte:	Bars Computer architecture Hardware Hardware > Electronic design automation > Methodologies for EDA Hardware > Emerging technologies Hardware > Hardware validation Hardware > Integrated circuits > Logic circuits > Arithmetic and datapath circuits Hardware > Integrated circuits > Logic circuits > Design modules and hierarchy Hardware > Very large scale integration design Instruction sets Microarchitecture Out of order Performance loss Pipeline processing Process design Processor scheduling
ISBN:	9780769531748, 0769531741
ISSN:	1063-6897
Online-Zugang:	Volltext
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