VEAL Virtualized Execution Accelerator for Loops

Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific accelerators used in conjunction with general purpose processors to achieve future performance goals. There is a serious drawback to accelerators, thou...

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Bibliographic Details
Published in:2008 International Symposium on Computer Architecture pp. 389 - 400
Main Authors: Clark, Nathan, Hormati, Amir, Mahlke, Scott
Format: Conference Proceeding
Language:English
Published: Washington, DC, USA IEEE Computer Society 01.06.2008
IEEE
Series:ACM Conferences
Subjects:
Acceleration
Algorithm design and analysis
Application software
Application specific integrated circuits
Computer aided instruction
Computer architecture
Costs
Energy consumption
Hardware
Hardware > Electronic design automation > Methodologies for EDA
Hardware > Integrated circuits > Logic circuits > Arithmetic and datapath circuits
Hardware > Integrated circuits > Logic circuits > Design modules and hierarchy
Hardware > Very large scale integration design > Application-specific VLSI designs > Application specific instruction set processors
Multicore processing
Software and its engineering > Software notations and tools > Compilers
Software and its engineering > Software notations and tools > Compilers > Runtime environments
Software and its engineering > Software notations and tools > General programming languages > Language features > Control structures
ISBN:9780769531748, 0769531741
ISSN:1063-6897
Online Access:Get full text
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Summary:Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific accelerators used in conjunction with general purpose processors to achieve future performance goals. There is a serious drawback to accelerators, though: binary compatibility. An application compiled to utilize an accelerator cannot run on a processor without that accelerator, and applications that do not utilize an accelerator will never use it. To overcome this problem, we propose decoupling the instruction set architecture from the underlying accelerators. Computation to be accelerated is expressed using a processor’s baseline instruction set, and light-weight dynamic translation maps the representation to whatever accelerators are available in the system. In this paper, we describe the changes to a compilation framework and processor system needed to support this abstraction for an important set of accelerator designs that support innermost loops. In this analysis, we investigate the dynamic overheads associated with abstraction as well as the static/dynamic tradeoffs to improve the dynamic mapping of loop-nests. As part of the exploration, we also provide a quantitative analysis of the hardware characteristics of effective loop accelerators. We conclude that using a hybrid static-dynamic compilation approach to map computation on to loop-level accelerators is an practical way to increase computation efficiency, without the overheads associated with instruction set modification.
ISBN:9780769531748
0769531741
ISSN:1063-6897
DOI:10.1109/ISCA.2008.33