Defect tolerant probabilistic design paradigm for nanotechnologies

Recent successes in the development and self-assembly of nanoelectronic devices suggest that the ability to manufacture dense nanofabrics is on the near horizon. However, the tremendous increase in device density of nanoelectronics will be accompanied by a substantial increase in hard and soft fault...

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Bibliographic Details
Published in:Proceedings - ACM IEEE Design Automation Conference pp. 596 - 601
Main Authors: Jacome, Margarida, He, Chen, de Veciana, Gustavo, Bijansky, Stephen
Format: Conference Proceeding
Language:English
Published: New York, NY, USA ACM 07.06.2004
IEEE
Series:ACM Conferences
Subjects:
Applied computing > Arts and humanities > Architecture (buildings) > Computer-aided design
Applied computing > Physical sciences and engineering > Engineering > Computer-aided design
Computer aided manufacturing
Costs
Design methodology
Helium
Nanoelectronics
Nanoscale devices
Scalability
Self-assembly
Silicon
Uncertainty
nanotechnologies
probabilistic design
defect tolerance
ISBN:1581138288, 9781581138283, 1511838288
ISSN:0738-100X
Online Access:Get full text
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Summary:Recent successes in the development and self-assembly of nanoelectronic devices suggest that the ability to manufacture dense nanofabrics is on the near horizon. However, the tremendous increase in device density of nanoelectronics will be accompanied by a substantial increase in hard and soft faults, posing a major challenge to current design methodologies and tools. In this paper we propose a novel probabilistic design paradigm for defective but reconfigurable nanofabrics. The new design goal is to devise an appropriate structural/behavioral decomposition which improves scalability by constraining the reconfiguration process, while meeting a desired probability of successful instantiation, i.e, yield. Our approach not only addresses the scalability problem in configuring dense nanofabrics subject to defects, but gives a rich framework in which critical trade-offs among performance, yield, and per chip cost can be explored. We present a concrete instance of the approach and show extensive experimental results supporting these claims.
ISBN:1581138288
9781581138283
1511838288
ISSN:0738-100X
DOI:10.1145/996566.996730