Scaling the power wall a path to exascale

Modern scientific discovery is driven by an insatiable demand for computing performance. The HPC community is targeting development of supercomputers able to sustain 1 ExaFlops by the year 2020 and power consumption is the primary obstacle to achieving this goal. A combination of architectural impro...

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Bibliographic Details
Published in:Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis pp. 830 - 841
Main Authors: Villa, Oreste, Johnson, Daniel R., O'Connor, Mike, Bolotin, Evgeny, Nellans, David, Luitjens, Justin, Sakharnykh, Nikolai, Wang, Peng, Micikevicius, Paulius, Scudiero, Anthony, Keckler, Stephen W., Dally, William J.
Format: Conference Proceeding
Language:English
Published: Piscataway, NJ, USA IEEE Press 16.11.2014
IEEE
Series:ACM Conferences
Subjects:
Bandwidth
Computer architecture
Computer systems organization > Architectures > Distributed architectures > Grid computing
Computer systems organization > Architectures > Parallel architectures > Multicore architectures
Computer systems organization > Architectures > Serial architectures > Superscalar architectures
Computer systems organization > Dependable and fault-tolerant systems and networks
Computing methodologies > Modeling and simulation > Simulation types and techniques > Massively parallel and high-performance simulations
General and reference > Cross-computing tools and techniques > Performance
Graphics processing units
Instruction sets
Kernel
Networks > Network performance evaluation
Registers
Software and its engineering > Software organization and properties > Software system structures > Distributed systems organizing principles > Grid computing
Supercomputers
ISBN:1479955000, 9781479955008
ISSN:2167-4329
Online Access:Get full text
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Summary:Modern scientific discovery is driven by an insatiable demand for computing performance. The HPC community is targeting development of supercomputers able to sustain 1 ExaFlops by the year 2020 and power consumption is the primary obstacle to achieving this goal. A combination of architectural improvements, circuit design, and manufacturing technologies must provide over a 20× improvement in energy efficiency. In this paper, we present some of the progress NVIDIA Research is making toward the design of Exascale systems by tailoring features to address the scaling challenges of performance and energy efficiency. We evaluate several architectural concepts for a set of HPC applications demonstrating expected energy efficiency improvements resulting from circuit and packaging innovations such as low-voltage SRAM, low-energy signaling, and on-package memory. Finally, we discuss the scaling of these features with respect to future process technologies and provide power and performance projections for our Exascale research architecture.
ISBN:1479955000
9781479955008
ISSN:2167-4329
DOI:10.1109/SC.2014.73