A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

In this paper we introduce CACTI-D, a significant enhancement of CACTI 5.0. CACTI-D adds support for modeling of commodity DRAM technology and support for main memory DRAM chip organization. CACTI-D enables modeling of the complete memory hierarchy with consistent models all the way from SRAM based...

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Veröffentlicht in:2008 International Symposium on Computer Architecture S. 51 - 62
Hauptverfasser: Thoziyoor, Shyamkumar, Ahn, Jung Ho, Monchiero, Matteo, Brockman, Jay B., Jouppi, Norman P.
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: Washington, DC, USA IEEE Computer Society 01.06.2008
IEEE
Schriftenreihe:ACM Conferences
Schlagworte:
Application software
Bandwidth
cache
CACTI
Circuits
commodity DRAM
Computer architecture
Computing methodologies > Modeling and simulation > Model development and analysis
Computing methodologies > Modeling and simulation > Model development and analysis > Model verification and validation
Computing methodologies > Modeling and simulation > Model development and analysis > Modeling methodologies
Fabrication
Hardware > Hardware validation
Hardware > Integrated circuits > Semiconductor memory
Hardware > Integrated circuits > Semiconductor memory > Dynamic memory
LLC
Logic
logic-process based DRAM
Multicore processing
Propagation delay
Random access memory
SRAM
Stacking
logic-process based DRAM
LLC
cache
commodity DRAM
CACTI
SRAM
ISBN:9780769531748, 0769531741
ISSN:1063-6897
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Zusammenfassung:In this paper we introduce CACTI-D, a significant enhancement of CACTI 5.0. CACTI-D adds support for modeling of commodity DRAM technology and support for main memory DRAM chip organization. CACTI-D enables modeling of the complete memory hierarchy with consistent models all the way from SRAM based L1 caches through main memory DRAMs on DIMMs. We illustrate the potential applicability of CACTI-D in the design and analysis of future memory hierarchies by carrying out a last level cache study for a multicore multithreaded architecture at the 32nm technology node. In this study we use CACTI-D to model all components of the memory hierarchy including L1, L2, last level SRAM, logic process based DRAM or commodity DRAM L3 caches, and main memory DRAM chips. We carry out architectural simulation using benchmarks with large data sets and present results of their execution time, breakdown of power in the memory hierarchy, and system energy-delay product for the different system configurations. We find that commodity DRAM technology is most attractive for stacked last level caches, with significantly lower energy-delay products.
ISBN:9780769531748
0769531741
ISSN:1063-6897
DOI:10.1109/ISCA.2008.16