Verification of hardware implementations through correctness of their recursive definitions in PVS

An approach is introduced to formally verify the logical correctness of reconfigurable hardware implementations of algebraic operators. Since Hardware Description Languages describe circuits/systems in an imperative style and formalization tools use recursive specification languages, the kernel of o...

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Bibliographic Details
Published in:	2014 27th Symposium on Integrated Circuits and Systems Design (SBCCI) pp. 1 - 8
Main Authors:	Alves Almeida, Ariane, Arias-Garcia, Janier, Llanos, Carlos H., Ayala-Rincon, Mauricio
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.09.2014
Subjects:	Algorithm design and analysis Clocks Field programmable gate arrays Finite element analysis Formal Verification Hardware Hardware Verification Libraries Random access memory Recursive Definitions
Online Access:	Get full text
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Summary:	An approach is introduced to formally verify the logical correctness of reconfigurable hardware implementations of algebraic operators. Since Hardware Description Languages describe circuits/systems in an imperative style and formalization tools use recursive specification languages, the kernel of our approach is based on a conservative translation from imperative into recursive implementations. The main challenge of this approach is that proofs follow an inductive schema that is based on guaranteeing pre and post-conditions and preservation of invariants during all steps of the recursive execution such as in the Floyd-Hoare's logical approach for verification of imperative procedures. The applicability of the methodology is illustrated in the Prototype Verification System (PVS) by proving the logical correctness of an FPGA implementation of the Gauss-Jordan matrix inversion algorithm (GJ). Correctness of this FPGA implementation is based on proving its functional equivalence (FEq) with an algebraic imperative definition of GJ. The approach allows formal verification of fragments of the implementations either simultaneously or afterwards the design process has been finished, avoiding in this way hardware development delays.
DOI:	10.1145/2660540.2660982