A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture

Processor architectures that are capable to reconfigure their instruction set and instruction format dynamically at run time offer a new flexibility exploiting instruction level parallelism vs. thread level parallelism. Based on the characteristics of an application or thread the instruction set arc...

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Vydané v:	Proceedings of the Conference on Design, Automation and Test in Europe s. 21 - 26
Hlavní autori:	Stripf, Timo, Koenig, Ralf, Becker, Juergen
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	San Jose, CA, USA EDA Consortium 12.03.2012
Edícia:	ACM Conferences
Predmet:	Computer systems organization > Architectures > Parallel architectures > Very long instruction word Computer systems organization > Architectures > Serial architectures > Complex instruction set computing Computer systems organization > Architectures > Serial architectures > Reduced instruction set computing Hardware > Very large scale integration design > Application-specific VLSI designs > Application specific instruction set processors
ISBN:	3981080181, 9783981080186
On-line prístup:	Získať plný text
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