A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS

A 5.3 times smaller and 2.6 times more energy-efficient all-digital wired-logic processor which infers MNIST with 90.6% accuracy and 1.2nJ of energy consumption has been developed. To improve area efficiency of wired-logic architecture, nonlinear neural network (NNN), which is a neuron and synapse e...

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Veröffentlicht in:Proceedings of the 28th Asia and South Pacific Design Automation Conference S. 180 - 181
Hauptverfasser: Sumikawa, Rei, Shiba, Kota, Kosuge, Atsutake, Hamada, Mototsugu, Kuroda, Tadahiro
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: New York, NY, USA ACM 16.01.2023
Schriftenreihe:ACM Conferences
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ISBN:9781450397834, 1450397832
Online-Zugang:Volltext
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Zusammenfassung:A 5.3 times smaller and 2.6 times more energy-efficient all-digital wired-logic processor which infers MNIST with 90.6% accuracy and 1.2nJ of energy consumption has been developed. To improve area efficiency of wired-logic architecture, nonlinear neural network (NNN), which is a neuron and synapse efficient network, and logical compression technology to implement it with area-saving and low-power digital circuits by logic synthesis are proposed, and asynchronous digital combinational circuit DNN hardware has been developed.
ISBN:9781450397834
1450397832
DOI:10.1145/3566097.3567941