Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems

A multi-FPGA system consists of multiple FPGAs connected by physical wires, and a circuit is partitioned to fit each FPGA and routed on the system by such physical wires. Due to the limited numbers of input/output (I/O) pins in an FPGA, however, not all signals can be transmitted between FPGAs direc...

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Vydané v:	2021 58th ACM/IEEE Design Automation Conference (DAC) s. 1129 - 1134
Hlavní autori:	Chen, Ming-Hung, Chang, Yao-Wen, Wang, Jun-Jie
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 05.12.2021
Predmet:	Delays Design automation Partitioning algorithms Pins Routing Time division multiplexing Wires
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