Characterizing the resource-sharing levels in the UltraSPARC T2 processor

Thread level parallelism (TLP) has become a popular trend to improve processor performance, overcoming the limitations of extracting instruction level parallelism. Each TLP paradigm, such as Simultaneous Multithreading or Chip-Multiprocessors, provides different benefits, which has motivated process...

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Veröffentlicht in:	2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) S. 481 - 492
Hauptverfasser:	Čakarević, Vladimir, Radojković, Petar, Verdú, Javier, Pajuelo, Alex, Cazorla, Francisco J., Nemirovsky, Mario, Valero, Mateo
Format:	Tagungsbericht Verlag
Sprache:	Englisch
Veröffentlicht:	New York, NY, USA ACM 12.12.2009 IEEE Association for Computing Machinery (ACM)
Schriftenreihe:	ACM Conferences
Schlagworte:	Arquitectura de computadors Arquitectures paral·leles Chip scale packaging CMP CMT Computer systems organization > Architectures Computer systems organization > Dependable and fault-tolerant systems and networks General and reference > Cross-computing tools and techniques > Performance Hardware Informàtica Job Scheduling Load management Multithreading Networks > Network performance evaluation Operating systems Performance Characterization Process design Processor scheduling Resource management Simultaneous Multithreading Simultaneous multithreading processors Sun Sun Nigara T2 UltraSPARC T2 Yarn Àrees temàtiques de la UPC performance characterization Sun Nigara T2 simultaneous multithreading CMT job scheduling CMP
ISBN:	9781605587981, 1605587982
ISSN:	1072-4451
Online-Zugang:	Volltext
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