Power-centric design of high-speed I/Os

With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is constrained by a complex set of specifications such as voltage levels, voltage noise, signal deterministic jitter, random jitt...

Full description

Saved in:
Bibliographic Details
Published in:2006 43rd ACM/IEEE Design Automation Conference pp. 867 - 872
Main Authors: Hatamkhani, Hamid, Lambrecht, Frank, Stojanovic, Vladimir, Yang, Chih-Kong Ken
Format: Conference Proceeding
Language:English
Published: New York, NY, USA ACM 24.07.2006
IEEE
Series:ACM Conferences
Subjects:
ISBN:1595933816, 9781595933812
ISSN:0738-100X
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is constrained by a complex set of specifications such as voltage levels, voltage noise, signal deterministic jitter, random jitter, slew rate, BER etc. These specifications lead to complex tradeoffs for both circuits and circuit architecture in order to minimize power. This paper presents a design framework that enables the analysis of tradeoffs in the design of an I/O transmitter. The design framework includes BER analysis with a channel model coupled with logic sizing optimization that is constrained by the desired signaling specification.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:1595933816
9781595933812
ISSN:0738-100X
DOI:10.1145/1146909.1147130