Power-centric design of high-speed I/Os

With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is constrained by a complex set of specifications such as voltage levels, voltage noise, signal deterministic jitter, random jitt...

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Vydáno v:2006 43rd ACM/IEEE Design Automation Conference s. 867 - 872
Hlavní autoři: Hatamkhani, Hamid, Lambrecht, Frank, Stojanovic, Vladimir, Yang, Chih-Kong Ken
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: New York, NY, USA ACM 24.07.2006
IEEE
Edice:ACM Conferences
Témata:
Aggregates
Algorithms
Bandwidth
Bit error rate
Channel Model
Circuit noise
Convex Optimization
Design
Hardware > Emerging technologies
Hardware > Integrated circuits > Interconnect > Input > output circuits
Hardware > Very large scale integration design
I/O
Jitter
Noise level
Power dissipation
Power Minimization
Serial Link
Signal design
Standardization
Transmitters
Voltage
power minimization
I/O
convex optimization
serial link
channel model
ISBN:1595933816, 9781595933812
ISSN:0738-100X
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Popis
Shrnutí:With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is constrained by a complex set of specifications such as voltage levels, voltage noise, signal deterministic jitter, random jitter, slew rate, BER etc. These specifications lead to complex tradeoffs for both circuits and circuit architecture in order to minimize power. This paper presents a design framework that enables the analysis of tradeoffs in the design of an I/O transmitter. The design framework includes BER analysis with a channel model coupled with logic sizing optimization that is constrained by the desired signaling specification.
Bibliografie:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:1595933816
9781595933812
ISSN:0738-100X
DOI:10.1145/1146909.1147130