Power-centric design of high-speed I/Os

With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is constrained by a complex set of specifications such as voltage levels, voltage noise, signal deterministic jitter, random jitt...

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Veröffentlicht in:	2006 43rd ACM/IEEE Design Automation Conference S. 867 - 872
Hauptverfasser:	Hatamkhani, Hamid, Lambrecht, Frank, Stojanovic, Vladimir, Yang, Chih-Kong Ken
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	New York, NY, USA ACM 24.07.2006 IEEE
Schriftenreihe:	ACM Conferences
Schlagworte:	Aggregates Algorithms Bandwidth Bit error rate Channel Model Circuit noise Convex Optimization Design Hardware > Emerging technologies Hardware > Integrated circuits > Interconnect > Input > output circuits Hardware > Very large scale integration design I/O Jitter Noise level Power dissipation Power Minimization Serial Link Signal design Standardization Transmitters Voltage power minimization I/O convex optimization serial link channel model
ISBN:	1595933816, 9781595933812
ISSN:	0738-100X
Online-Zugang:	Volltext
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